There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), complementary metal oxide semiconductor devices (CMOS), photodiode arrays, charge injection devices and hybrid focal plane arrays. Among these, CCDs and CMOS imagers are the most commonly used in digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television. Each type of imaging device has advantages and disadvantages relative to the other.
CCDs imagers have a greater sensitivity to light and have better dynamic range than CMOS imagers, and therefore yield superior quality images. CCDs are also capable of large formats with small pixel size, and produces less noise (visual artifacts). As a result of these advantages, CCDs are the preferred technology for high end imaging applications.
However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, exhibit destructive read out over time, require good light shielding to avoid image smear, and have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing due in part to a different processing technology and to their high capacitances, which complicates the integration of on-chip drive and signal processing electronics with the CCD array. Further in this regard, CCDs must be manufactured at one of a small number of specialized fabrication facilities, thus greatly increasing production costs and limiting economies of scale. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer, which results in image smear.
On the other hand, CMOS imagers have the advantage of being compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion). On-chip integration of electronics provides the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a compact system size. CMOS imagers also allow random access to the image data, and have low fabrication costs as compared with CCD imagers since standard CMOS processing techniques can be used. Additionally, CMOS imagers have low voltage operation and low power consumption because only one row of pixels at a time needs to be active during readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition.
Both CCD and CMOS imagers perform the necessary functions of (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of the accumulated image charge; (4) converting the accumulated image charge to a voltage; and (5) output and amplification of the signal voltage representing the charge from each pixel in the imager. Both CCD and CMOS imagers include an array of pixels, each pixel having a substrate and a photosensitive area formed in or on the substrate and which converts photons from the incident light into charge, either electrons or holes. CCD and CMOS imagers differ, however, in their structure and manner of processing accumulated charges after photon to charge conversion.
The basic structure of a pixel within a CCD imager is shown in FIG. 1 and includes a silicon substrate 10, a thin film of insulating material 11 such as silicon dioxide overlying the substrate surface, and a plurality of gate electrodes 12a formed of a conductive material, such as doped polysilicon, formed spaced apart from each other on top of the layer of insulating material 11. As shown in FIG. 1, additional gate electrodes 12b are formed between and overlapping electrodes 12a. Gate electrodes 12b may also be formed of doped polysilicon. An insulator layer 9 is formed over the surface of electrodes 12a prior to forming the overlapping electrodes 12b to prevent shorting between electrodes 12a and 12b. 
Substrate 10 includes a buried channel 8 formed in the substrate 10 under the electrodes 12a, 12b. Typically in a CCD imager, the substrate is doped p-type, whereupon the buried channel is doped n-type. When a voltage is applied to gate electrode 12b, for example, photons from the incident light are converted to electrical charge in the buried channel 8 under the “activated” gate 12b, and a well 13 is formed in the substrate in which the charge is accumulated under the activated gate 12b. Charge is contained in the well by applying appropriate voltages to the gate electrodes 12a surrounding the activated gate to form zones of higher potential surrounding the well 13, thus confining the accumulated charge in the well 13.
The accumulated charge is transferred out of the pixel by “moving” the well from one gate electrode 12 to another in the pixel by alternating the voltages applied to the different electrodes until the charge is moved out of the pixel. In this manner, the pixel charges are moved through the array 15 row by row (FIG. 2). Movement of charge through each pixel and the array is controlled by a clock signal PCLK inputted to each pixel in the array. When the charges reach the last row 17 in the array 15, the charges are moved horizontally through the row according to the serial clock signal SCLK. After each charge moves through the last pixel position in the last row 17 of the array 15, the charge is passed through an output amplifier 21 to produce an analog voltage representing the amount of charge, and then is outputted from the pixel array 15. Once each pixel signal exits the pixel array, the analog voltage signal is converted to a digital signal in analog-to-digital converter 23. From there, the digital pixel signal is passed to the image processor 25 for compiling the pixel signals into a digital image.
Depending on the number of gates in each pixel within a particular CCD architecture, a complete charge transfer cycle may be completed for each pixel in four phases, three phases or two phases, in accordance with the clock signal PCLK. For example, a timing diagram for a four phase CCD is shown in FIG. 3. In this pixel, integration time occurs at t1 when the voltage on the φ1 and φ2 gates are held at a high level to form low potential zones while the voltages of the φ3 and φ4 gates are held at a low level to form high potential barriers. During this time, photo-induced charge is collected in a potential well which is formed under the φ1 and φ2 gates. The well is then moved under the φ2 and φ3 gates by applying a high voltage to the φ2 and φ3 gates and a low voltage to the φ1 and φ4 gates at time t2. At time t3, the well is similarly moved under the φ3 and φ4 gates, and eventually under the φ1 and φ2 gates of the next pixel. In this manner, all the collected charge in the pixel array during one integration period is moved through the array until outputted to output amplifier 21.
An exemplary CMOS imager is described below with reference to FIG. 4. The circuit described below, for example, includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. However, it should be understood that the photosensitive element of a CMOS imager pixel may alternatively be formed as a depleted p-n junction photodiode, a photoconductor, or other image-to-charge converting device, in lieu of a field induced depletion region beneath a photogate. It is noted that photodiodes may experience the disadvantage of image lag, which can be eliminated if the photodiode is completely depleted upon readout.
Like a CCD imager, the CMOS imager includes a focal plane array of pixel cells. As shown in FIG. 4, a simplified circuit for a pixel of an exemplary CMOS imager includes a pixel photodetector circuit 14 and a readout circuit 60. It should be understood that while FIG. 4 shows the circuitry for operation of a single pixel, that in practical use there will be an M×N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodetector circuit 14 is shown in part as a cross-sectional view of a semiconductor substrate 16 formed typically of a p-type silicon, and having a surface well of p-type material 20. An optional layer 18 of p-type material may be used if desired, but is not required. Substrate 16 may be formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entire substrate 16 is a p-type doped silicon substrate and may contain a surface p-well 20 (with layer 18 omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates, or the like.
An insulating layer 22 of silicon dioxide, silicon nitride or other suitable material is formed on the upper surface of p-well 20. A photogate 24 thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer 22. The photogate 24 receives an applied control signal PG which causes the initial accumulation of pixel charges underneath the photogate 24 and in n+ region 26. The n+ type region 26, adjacent one side of photogate 24, is formed in the upper surface of p-well 20.
A transfer gate 28 is formed on insulating layer 22 between n+ type region 26 and a second n+ type region 30 formed in p-well 20. The n+ regions 26 and 30 and transfer gate 28 form a charge transfer transistor 29 which is controlled by a transfer signal TX. When a transfer signal TX is applied to the transfer gate 28, the charge accumulated in n+ region 26 is transferred into n+ region 30. The n+ region 30 is typically called a floating diffusion node, and is also a node for passing charge accumulated thereat to the gate of a source follower transistor 36 described below.
A reset gate 32 is also formed on insulating layer 22 adjacent and between n+ type node 30 and another n+ region 34 which is also formed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form a reset transistor 31 which is controlled by a reset signal RST. The n+ type region 34 is coupled to voltage source VDD. The transfer and reset transistors 29, 31 are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well, in which case each of the transistors would be p-channel transistors. It should also be noted that while FIG. 4 shows the use of a transfer gate 28 and associated transistor 29, this structure provides advantages, but is not required.
Photodetector circuit 14 also includes two additional n-channel transistors, source follower transistor 36 and row select transistor 38. Transistors 36 and 38 are coupled in series, source to drain, with the source of transistor 36 also coupled over lead 40 to voltage source VDD and the drain of transistor 38 coupled to a lead 42. The gate of transistor 36 is coupled over lead 44 to n+ region 30. Charge from the floating diffusion node at the n+ region 30 is typically converted to a pixel output voltage by the source follower output transistor 36. The drain of row select transistor 38 is connected via conductor 42 to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor 39 is also coupled between the drain of transistor 38 and a voltage source VSS. Transistor 39 is kept on by a signal VLN applied to its gate.
The imager includes a readout circuit 60 which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor 62 and a signal storage capacitor 64 connected to the source follower transistor 36 through row transistor 38. The other side of the capacitor 64 is connected to a source voltage VSS. The upper side of the capacitor 64 is also connected to the gate of a p-channel output transistor 66. The drain of the output transistor 66 is connected through a column select transistor 68 to a signal sample output node VOUTS and through a load transistor 70 to the voltage supply VDD. A sample and hold signal (SHS) briefly turns on the S/H transistor 62 after the charge accumulated beneath the photogate electrode 24 has been transferred to the floating diffusion node 30, and from there, to the source follower transistor 36 and through row select transistor 38 to line 42, so that the capacitor 64 stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode 24.
The readout circuit 60 also includes a reset sample and hold (S/H) circuit including a S/H transistor 72 and a signal storage capacitor 74 connected through the S/H transistor 72 and through the row select transistor 38 to the source of the source follower transistor 36. The bottom side of the capacitor 74 is connected to the source voltage VSS. The upper side of the capacitor 74 is also connected to the gate of a p-channel output transistor 76. The drain of the output transistor 76 is connected through a p-channel column select transistor 78 to a reset sample output node VOUTR and through a load transistor 80 to the supply voltage VDD. A sample and hold reset signal (SHR) briefly turns on the S/H transistor 72 immediately after the reset signal RST has caused reset transistor 31 to turn on and reset the potential of the floating diffusion node 30, so that the capacitor 74 stores the voltage to which the floating diffusion node 30 has been reset.
The readout circuit 60 provides correlated sampling of the potential of the floating diffusion node 30, first of the reset charge applied to node 30 by reset transistor 31 and then of the stored charge from the photogate 24. The two samplings of the diffusion node 30 charges produce respective output voltages VOUTR and VOUTS of the readout circuit 60. These voltages are then subtracted (VOUTS-VOUTR) by subtractor 82 to provide an output signal terminal 81 which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor 31 which might cause pixel to pixel variations in the output signal.
FIG. 5 illustrates a block diagram for a CMOS imager having a pixel array 90 with each pixel cell being constructed in the manner shown by element 14 of FIG. 4. While pixel array 90 comprises a plurality of pixels arranged in a predetermined number of columns and rows, FIG. 6 shows a 2×2 portion of pixel array 90 for illustrative purposes in this discussion. The pixels of each row in array 90 are and turned on at the same time by a row select line, e.g., line 86, and the pixels of each column are selectively output by a column select line, e.g., line 42. A plurality of rows and column lines are provided for the entire array 90. The row lines are selectively activated by the row driver 92 in response to row address decoder 94 and the column select lines are selectively activated by the column driver 96 in response to column address decoder 98. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit 95 which controls address decoders 94, 98 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 92, 96 which apply driving voltage to the drive transistors of the selected row and column lines.
FIG. 7 shows a simplified timing diagram for the signals used to transfer charge out of photodetector circuit 14 of the FIG. 4 CMOS imager. The photogate signal PG is nominally set to 5V and the reset signal RST is nominally set at 2.5V. As can be seen from the figure, the process is begun at time to by briefly pulsing reset voltage RST to 5V. The RST voltage, which is applied to the gate 32 of reset transistor 31, causes transistor 31 to turn on and the floating diffusion node 30 to charge to the VDD voltage present at n+ region 34 (less the voltage drop Vth of transistor 31). This resets the floating diffusion node 30 to a predetermined voltage (VDD−Vth). The charge on floating diffusion node 30 is applied to the gate of the source follower transistor 36 to control the current passing through transistor 38, which has been turned on by a row select (ROW) signal, and load transistor 39. This current is translated into a voltage on line 42 which is next sampled by providing a SHR signal to the S/H transistor 72, which charges capacitor 74 with the source follower transistor output voltage on line 42 representing the reset charge present at floating diffusion node 30. The PG signal is next pulsed to 0 volts, causing charge to be collected in n+ region 26.
A transfer gate voltage pulse TX, similar to the reset pulse RST, is then applied to transfer gate 28 of transistor 29 to cause the charge in n+ region 26 to transfer to floating diffusion node 30. It should be understood that for the case of a photogate, the transfer gate voltage TX may be pulsed or held to a fixed DC potential. For the implementation of a photodiode with a transfer gate, the transfer gate voltage TX must be pulsed. The new output voltage on line 42 generated by source follower transistor 36 current is then sampled onto capacitor 64 by enabling the sample and hold switch 62 with signal SHS. The column select signal is next applied to transistors 68 and 70 and the respective charges stored in capacitors 64 and 74 are subtracted in subtractor 82 to provide a pixel output signal at terminal 81. It should also be understood that CMOS imagers may dispense with the transistor gate 28 and associated transistor 29, or retain these structures while biasing the transfer transistor gate 28 to an always “on” state.
Both CMOS and CCD imagers are susceptible to inefficient charge transfer between gates. In the CMOS imager shown in FIG. 4, the presence of an n+ region 26 is necessary to electrically couple the photogate 24 to the transfer gate 28 across the relatively wide gap, eg., 0.25 microns, separating the transfer gate 28 and the photogate 24. When a signal TX is applied to the transfer gate 28, the n+ region 26 functions as a conducting channel to pass charges from the doped layer under the photogate into the channel region of the transfer transistor 29, and then to the floating diffusion node 30. Incorporation of the n+ region 26, however, produces excess noise and incomplete charge transfer between gates. Similarly, in CCD imagers, it is known that the transfer of charge from gate to gate and pixel to pixel is never 100% efficient.
In order to improve the charge transfer between gates in both CMOS and CCD imagers, the gates must be spaced as close together as possible. The gates are formed by depositing a single layer of polysilicon (or other suitable conductive material) on the substrate surface (over the insulating layer such as silicon dioxide, silicon nitride, etc.). The individual gates are then patterned from the blanket deposited layer by applying a layer of photoresist over the polysilicon (or other conductive) material, and exposing the photoresist through a reticle to develop the portions of the photoresist where the gates are to be formed. The undeveloped portions of the photoresist are then removed. Once the shaped photoresist layer has been obtained on the blanket deposited layer of conductive material, the gates are shaped by etching the layer of conductive material around the patterned photoresist layer.
The smallest distance between semiconductor structures using known patterning methods such as that mentioned above is subject to the physical limitations of how thin a distinguishable line or gap can be formed in the photoresist layer by patterning with the reticle. Recent advances in technology enable lines and spaces between semiconductor structures to be 0.13 micrometers apart, i.e., about 1300 Angstroms. Even with these measurements, however, the resulting gaps between polysilicon gates still yield incomplete charge transfer.